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| 700 MHz to 2.7 GHz Quadrature Demodulator ADL5382 FEATURES Operating RF and LO frequency: 700 MHz to 2.7 GHz Input IP3 33.5 dBm @ 900 MHz 30.5 dBm @1900 MHz Input IP2: >70 dBm @ 900 MHz Input P1dB: 14.7 dBm @ 900 MHz Noise figure (NF) 14.0 dB @ 900 MHz 15.6 dB @ 1900 MHz Voltage conversion gain: ~4 dB Quadrature demodulation accuracy Phase accuracy: ~0.2 Amplitude balance: ~0.05 dB Demodulation bandwidth: ~370 MHz Baseband I/Q drive: 2 V p-p into 200 Single 5 V supply FUNCTIONAL BLOCK DIAGRAM CMRF CMRF RFIP RFIN CMRF VPX 24 VPA COM BIAS VPL VPL VPL 1 2 3 4 5 6 7 CML 8 9 10 11 CML 12 COM 0 90 23 22 21 20 19 18 VPB 17 VPB 16 QHI 15 QLO 14 IHI 13 ILO 07208-001 ADL5382 BIAS GEN LOIP LOIN CML Figure 1. APPLICATIONS Cellular W-CDMA/CDMA/CDMA2000/GSM Microwave point-to-(multi)point radios Broadband wireless and WiMAX GENERAL DESCRIPTION The ADL5382 is a broadband quadrature I-Q demodulator that covers an RF input frequency range from 700 MHz to 2.7 GHz. With a NF = 14 dB, IP1dB = 14.7 dBm, and IIP3 = 33.5 dBm at 900 MHz, the ADL5382 demodulator offers outstanding dynamic range suitable for the demanding infrastructure direct-conversion requirements. The differential RF inputs provide a well-behaved broadband input impedance of 50 and are best driven from a 1:1 balun for optimum performance. Excellent demodulation accuracy is achieved with amplitude and phase balances ~0.05 dB and ~0.2, respectively. The demodulated in-phase (I) and quadrature (Q) differential outputs are fully buffered and provide a voltage conversion gain of ~4 dB. The buffered baseband outputs are capable of driving a 2 V p-p differential signal into 200 . The fully balanced design minimizes effects from second-order distortion. The leakage from the LO port to the RF port is <-65 dBc. Differential dc offsets at the I and Q outputs are typically <10 mV. Both of these factors contribute to the excellent IIP2 specifications which is >60 dBm. The ADL5382 operates off a single 4.75 V to 5.25 V supply. The supply current is adjustable with an external resistor from the BIAS pin to ground. The ADL5382 is fabricated using the Analog Devices, Inc., advanced Silicon-Germanium bipolar process and is available in a 24-lead exposed paddle LFCSP. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved. ADL5382 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Distributions for fRF = 900 MHz ............................................... 10 Distributions for fRF = 1900 MHz............................................. 11 Distributions for fRF = 2700 MHz............................................. 12 Circuit Description......................................................................... 13 LO Interface................................................................................. 13 V-to-I Converter......................................................................... 13 Mixers .......................................................................................... 13 Emitter Follower Buffers ........................................................... 13 Bias Circuit.................................................................................. 13 Applications Information .............................................................. 14 Basic Connections...................................................................... 14 Power Supply............................................................................... 14 Local Oscillator (LO) Input ...................................................... 14 RF Input....................................................................................... 15 Baseband Outputs ...................................................................... 15 Error Vector Magnitude (EVM) Performance........................... 16 Low IF Image Rejection............................................................. 17 Example Baseband Interface..................................................... 17 Characterization Setups................................................................. 21 Evaluation Board ............................................................................ 23 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 27 REVISION HISTORY 3/08--Revision 0: Initial Version Rev. 0 | Page 2 of 28 ADL5382 SPECIFICATIONS VS = 5 V, TA = 25C, fLO = 900 MHz, fIF = 4.5 MHz, PLO = 0 dBm, BIAS pin open, ZO = 50 , unless otherwise noted. Baseband outputs differentially loaded with 450 . Loss of the balun used to drive the RF port was de-embedded from these measurements. Table 1. Parameter OPERATING CONDITIONS LO and RF Frequency Range LO INPUT Input Return Loss LO Input Level I/Q BASEBAND OUTPUTS Voltage Conversion Gain Demodulation Bandwidth Quadrature Phase Error I/Q Amplitude Imbalance Output DC Offset (Differential) Output Common Mode 0.1 dB Gain Flatness Output Swing Peak Output Current POWER SUPPLIES Voltage Current DYNAMIC PERFORMANCE at RF = 900 MHz Conversion Gain Input P1dB Second-Order Input Intercept (IIP2) Third-Order Input Intercept (IIP3) LO to RF RF to LO IQ Magnitude Imbalance IQ Phase Imbalance LO to IQ Noise Figure Noise Figure under Blocking Conditions DYNAMIC PERFORMANCE at RF = 1900 MHz Conversion Gain Input P1dB Second-Order Input Intercept (IIP2) Third-Order Input Intercept (IIP3) LO to RF RF to LO IQ Magnitude Imbalance IQ Phase Imbalance LO to IQ Noise Figure Noise Figure under Blocking Conditions Condition Min 0.7 LOIP, LOIN LO driven differentially through a balun at 900 MHz -6 QHI, QLO, IHI, ILO 450 differential load on I and Q outputs at 900 MHz 200 differential load on I and Q outputs at 900 MHz 1 V p-p signal, 3 dB bandwidth At 900 MHz 0 dBm LO input at 900 MHz -11 0 3.9 3.0 370 0.2 0.05 5 VPOS - 2.8 50 2 12 4.75 BIAS pin open RBIAS = 4 k 220 196 3.9 14.7 73 33.5 -92 -89 0.05 0.2 -43 14.0 19.9 3.9 14.4 65 30.5 -71 -78 0.05 0.2 -41 15.6 20.5 5.25 Typ Max 2.7 Unit GHz dB dBm dB dB MHz Degrees dB mV V MHz V p-p mA V mA mA dB dBm dBm dBm dBm dBc dB Degrees dBm dB dB dB dBm dBm dBm dBm dBc dB Degrees dBm dB dB +6 Differential 200 load Each pin VPA, VPL, VPB, VPX -5 dBm each input tone -5 dBm each input tone RFIN, RFIP terminated in 50 LOIN, LOIP terminated in 50 RFIN, RFIP terminated in 50 With a -5 dBm interferer 5 MHz away -5 dBm each input tone -5 dBm each input tone RFIN, RFIP terminated in 50 LOIN, LOIP terminated in 50 RFIN, RFIP terminated in 50 With a -5 dBm interferer 5 MHz away Rev. 0 | Page 3 of 28 ADL5382 Parameter DYNAMIC PERFORMANCE at RF = 2700 MHz Conversion Gain Input P1dB Second-Order Input Intercept (IIP2) Third-Order Input Intercept (IIP3) LO to RF RF to LO IQ Magnitude Imbalance IQ Phase Imbalance LO to IQ Noise Figure Condition RFIP, RFIN Min Typ 3.3 14.5 52 28.3 -70 -55 0.16 0.1 -42 17.6 Max Unit dB dBm dBm dBm dBm dBc dB Degrees dBm dB -5 dBm each input tone -5 dBm each input tone RFIN, RFIP terminated in 50 , 1xLO appearing at RF port LOIN, LOIP terminated in 50 RFIN, RFIP terminated in 50 , 1xLO appearing at BB port Rev. 0 | Page 4 of 28 ADL5382 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage (VPA, VPL, VPB, VPX) LO Input Power RF Input Power Internal Maximum Power Dissipation JA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating 5.5 V 13 dBm (re: 50 ) 15 dBm (re: 50 ) 1230 mW 54C/W 150C -40C to +85C -65C to +125C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. 0 | Page 5 of 28 ADL5382 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 24 1 2 3 4 5 6 23 22 21 20 19 CMRF CMRF RFIP RFIN CMRF VPX VPA VPB 18 COM BIAS VPL VPL VPL CML 7 LOIP LOIN CML 8 9 10 CML 11 VPB 17 QHI 16 QLO 15 IHI 14 ILO 13 12 07208-002 ADL5382 TOP VIEW (Not to Scale) COM Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 4 to 6, 17 to 19 2, 7, 10 to 12, 20, 23, 24 3 8, 9 13 to 16 Mnemonic VPA, VPL, VPB, VPX COM, CML, CMRF BIAS LOIP, LOIN ILO, IHI, QLO, QHI Description Supply. Positive supply for LO, IF, biasing, and baseband sections. These pins should be decoupled to the board ground using appropriate-sized capacitors. Ground. Connect to a low impedance ground plane. Bias Control. A resistor (RBIAS) can be connected between BIAS and COM to reduce the mixer core current. The default setting for this pin is open. Local Oscillator Input. Pins must be ac-coupled. A differential drive through a balun (recommended balun is the M/A-COM ETC1-1-13) is necessary to achieve optimal performance. I Channel and Q Channel Mixer Baseband Outputs. These outputs have a 50 differential output impedance (25 per pin). The bias level on these pins is equal to VPOS - 2.8 V. Each output pair can swing 2 V p-p (differential) into a load of 200 . Output 3 dB bandwidth is 370 MHz. RF Input. A single-ended 50 signal can be applied to the RF inputs through a 1:1 balun (recommended balun is the M/A-COM ETC1-1-13). Ground-referenced inductors must also be connected to RFIP and RFIN (recommended values = 33 nH). Exposed Paddle. Connect to a low impedance thermal and electrical ground plane. 21, 22 RFIN, RFIP EP Rev. 0 | Page 6 of 28 ADL5382 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, TA = 25C, LO drive level = 0 dBm, RBIAS = open, RF input balun loss is de-embedded, unless otherwise noted. 20 TA = -40C TA = +25C TA = +85C 2 1 0 INPUT P1dB GAIN (dB), IP1dB (dBm) 15 BASEBAND RESPONSE (dB) 07208-003 -1 -2 -3 -4 -5 -6 -7 07208-006 07208-008 07208-007 10 GAIN 5 0 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) -8 10 100 BASEBAND FREQUENCY (MHz) 1000 Figure 3. Conversion Gain and Input IP1 dB Compression Point (IP1dB) vs. RF Frequency 80 70 60 INPUT IP2 I CHANNEL Q CHANNEL Figure 6. Normalized IQ Baseband Frequency Response 19 18 17 16 15 14 13 12 700 TA = -40C TA = +25C TA = +85C 50 40 30 20 10 700 INPUT IP3 (I AND Q CHANNELS) TA = -40C TA = +25C TA = +85C 07208-004 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) NOISE FIGURE (dB) IIP3, IIP2 (dBm) 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) Figure 4. Input Third-Order Intercept (IIP3) and Input Second-Order Intercept Point (IIP2) vs. RF Frequency 2.0 1.5 1.0 4 Figure 7. Noise Figure vs. RF Frequency QUADRATURE PHASE ERROR (Degrees) 3 2 1 0 -1 -2 -3 -4 700 TA = -40C TA = +25C TA = +85C GAIN MISMATCH (dB) 0.5 0 -0.5 -1.0 -1.5 -2.0 700 TA = -40C TA = +25C TA = +85C 07208-005 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) Figure 5. IQ Gain Mismatch vs. RF Frequency Figure 8. IQ Quadrature Phase Error vs. RF Frequency Rev. 0 | Page 7 of 28 ADL5382 GAIN (dB), IP1dB (dBm), NOISE FIGURE (dB) 20 IIP2, Q CHANNEL IIP2, I CHANNEL 15 NOISE FIGURE 10 50 80 GAIN (dB), IP1dB (dBm), NOISE FIGURE (dB) 20 IIP2, Q CHANNEL 18 16 14 NOISE FIGURE 12 10 8 6 4 2 0 -6 GAIN IIP3 IP1dB IIP2, I CHANNEL 75 IP1dB 65 65 45 35 5 IIP3 35 25 GAIN 0 -6 20 LO LEVEL (dBm) LO LEVEL (dBm) Figure 9. Conversion Gain, IP1dB, Noise Figure, IIP3, and IIP2 vs. LO Level, fRF = 900 MHz 34 TA = -40C TA = +25C TA = +85C SUPPLY CURRENT 26 INPUT IP3 250 240 230 220 210 22 200 18 NOISE FIGURE 14 170 10 160 100 190 180 IIP3 (dBm) AND NOISE FIGURE (dB) Figure 12. Conversion Gain, IP1dB, Noise Figure, IIP3, and IIP2 vs. LO Level, fRF = 1900 MHz 32 TA = -40C TA = +25C TA = +85C INPUT IP3 IIP3 (dBm) AND NOISE FIGURE (dB) 30 28 SUPPLY CURRENT (mA) 24 20 NOISE FIGURE 16 12 1 10 RBIAS (k) 100 RBIAS (k) Figure 10. IIP3, Noise Figure, and Supply Current vs. RBIAS, fRF = 900 MHz 29 27 25 80 70 Figure 13. IIP3 and Noise Figure vs. RBIAS, fRF = 1900 MHz GAIN (dB), IP1dB (dBm), IIP2 I AND Q CHANNEL (dBm) 60 50 40 30 20 10 0 900MHz: GAIN 900MHz: IP1dB 900MHz: IIP2, I CHANNEL 900MHz: IIP2, Q CHANNEL 1900MHz: GAIN 1900MHz: IP1dB 1900MHz: IIP2, I CHANNEL 1900MHz: IIP2, Q CHANNEL NOISE FIGURE (dB) 23 21 19 1900MHz 17 15 13 -30 900MHz RF BLOCKER INPUT POWER (dBm) RBIAS (k) Figure 11. Noise Figure vs. Input Blocker Level, fRF = 900 MHz, 1900 MHz (RF Blocker 5 MHz Offset) Figure 14. Conversion Gain, IP1dB, IIP2_I, and IIP2_Q vs. RBIAS, fRF = 900 MHz, 1900MHz Rev. 0 | Page 8 of 28 07208-014 -25 -20 -15 -10 -5 0 5 07208-011 1 10 100 07208-013 1 10 07208-010 8 07208-012 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 07208-009 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 15 IIP3, IIP2 (dBm) IIP3, IIP2 (dBm) 55 ADL5382 40 IIP3 35 30 I CHANNEL Q CHANNEL 85 -20 -30 IIP2, I AND Q CHANNELS (dBm) 80 -40 IP1dB, IIP3 (dBm) 25 20 15 10 5 0 TA = -40C TA = +25C TA = +85C 0 10 20 30 40 BASEBAND FREQUENCY (MHz) IP1dB IIP2 LEAKAGE (dBm) 75 -50 -60 -70 -80 -90 70 65 07208-015 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 LO FREQUENCY (MHz) Figure 15. IP1dB, IIP3, and IIP2 vs. Baseband Frequency 0 -10 -20 -20 -30 -40 LEAKAGE (dBc) Figure 18. LO-to-RF Leakage vs. LO Frequency LEAKAGE (dBm) -30 -40 -50 -60 -70 -80 700 -50 -60 -70 -80 -90 -100 700 07208-016 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 LO FREQUENCY (MHz) 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) Figure 16. LO-to-BB Leakage vs. LO Frequency 0 -5 -10 Figure 19. RF-to-LO Leakage vs. RF Frequency 0 -5 RETURN LOSS (dB) RETURN LOSS (dB) -15 -20 -25 -30 -35 -40 -45 07208-017 -10 -15 -20 -25 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 LO FREQUENCY (MHz) Figure 17. RF Port Return Loss vs. RF Frequency Measured on a Characterization Board through an ETC1-1-13 Balun with 33 nH Bias Inductors Figure 20. LO Port Return Loss vs. LO Frequency Measured on Characterization Board through an ETC1-1-13 Balun Rev. 0 | Page 9 of 28 07208-020 -50 700 -30 700 07208-019 07208-018 60 50 -100 700 ADL5382 DISTRIBUTIONS FOR fRF = 900 MHz 100 TA = -40C TA = +25C TA = +85C 100 TA = -40C TA = +25C TA = +85C 80 PERCENTAGE (%) 80 60 PERCENTAGE (%) 60 40 40 20 20 I CHANNEL Q CHANNEL 50 55 60 65 70 75 80 85 07208-024 07208-026 07208-025 31 32 33 34 INPUT IP3 (dBm) 35 36 37 07208-021 0 0 45 INPUT IP2 (dBm) Figure 21. IIP3 Distributions, fRF = 900 MHz 100 Figure 24. IIP2 Distributions for I Channel and Q Channel, fRF = 900 MHz 100 TA = -40C TA = +25C TA = +85C TA = -40C TA = +25C TA = +85C 80 80 PERCENTAGE (%) 60 PERCENTAGE (%) 12 13 14 15 16 17 07208-022 60 40 40 20 20 0 0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 INPUT P1dB (dBm) NOISE FIGURE (dB) Figure 22. IP1dB Distributions, fRF = 900 MHz 100 100 Figure 25. Noise Figure Distributions, fRF = 900 MHz TA = -40C TA = +25C TA = +85C TA = -40C TA = +25C TA = +85C 80 80 PERCENTAGE (%) 60 PERCENTAGE (%) -0.1 0 GAIN MISMATCH (dB) 0.1 0.2 07208-023 60 40 40 20 20 0 -0.2 0 -1.00 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 QUADRATURE PHASE ERROR (Degrees) Figure 23. IQ Gain Mismatch Distributions, fRF = 900 MHz Figure 26. IQ Quadrature Phase Error Distributions, fRF = 900 MHz Rev. 0 | Page 10 of 28 ADL5382 DISTRIBUTIONS FOR fRF = 1900 MHz 100 TA = -40C TA = +25C TA = +85C 100 TA = -40C TA = +25C TA = +85C 80 PERCENTAGE (%) PERCENTAGE (%) 80 60 60 40 40 20 20 I CHANNEL Q CHANNEL 50 55 60 65 70 75 80 85 07208-030 07208-032 07208-031 29 30 31 32 33 INPUT IP3 (dBm) 07208-027 0 28 0 45 INPUT IP2 (dBm) Figure 27. IIP3 Distributions, fRF = 1900 MHz 100 Figure 30. IIP2 Distributions for I Channel and Q Channel, fRF = 1900 MHz 100 TA = -40C TA = +25C TA = +85C TA = -40C TA = +25C TA = +85C 80 80 PERCENTAGE (%) 07208-028 PERCENTAGE (%) 60 60 40 40 20 20 0 12 13 14 15 16 17 0 14.0 14.5 15.0 15.5 16.0 16.5 17.0 INPUT P1dB (dBm) NOISE FIGURE (dB) Figure 28. IP1dB Distributions, fRF = 1900 MHz 100 TA = -40C TA = +25C TA = +85C Figure 31. Noise Figure Distributions, fRF = 1900 MHz 100 TA = -40C TA = +25C TA = +85C 80 80 PERCENTAGE (%) 07208-029 PERCENTAGE (%) 60 60 40 40 20 20 0 -0.2 -0.1 0 GAIN MISMATCH (dB) 0.1 0.2 0 -1.00 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 QUADRATURE PHASE ERROR (Degrees) Figure 29. IQ Gain Mismatch Distributions, fRF = 1900 MHz Figure 32. IQ Quadrature Phase Error Distributions, fRF = 1900 MHz Rev. 0 | Page 11 of 28 ADL5382 DISTRIBUTIONS FOR fRF = 2700 MHz 100 TA = -40C TA = +25C TA = +85C 100 TA = -40C TA = +25C TA = +85C 80 PERCENTAGE (%) PERCENTAGE (%) 80 60 60 40 40 20 20 I CHANNEL Q CHANNEL 50 55 60 65 70 75 80 85 07208-036 07208-038 07208-037 27 28 29 30 31 INPUT IP3 (dBm) 07208-033 0 26 0 45 INPUT IP2 (dBm) Figure 33. IIP3 Distributions, fRF = 2700 MHz 100 Figure 36. IIP2 Distributions for I Channel and Q Channel, fRF = 2700 MHz 100 TA = -40C TA = +25C TA = +85C TA = -40C TA = +25C TA = +85C 80 80 PERCENTAGE (%) 60 PERCENTAGE (%) 13 14 15 16 17 07208-034 60 40 40 20 20 0 12 0 16.0 16.5 17.0 17.5 18.0 18.5 19.0 INPUT P1dB (dBm) NOISE FIGURE (dB) Figure 34. IP1dB Distributions, fRF = 2700 MHz 100 100 Figure 37. Noise Figure Distributions, fRF = 2700 MHz TA = -40C TA = +25C TA = +85C TA = -40C TA = +25C TA = +85C 80 PERCENTAGE (%) PERCENTAGE (%) 80 60 60 40 40 20 20 0 0.1 GAIN MISMATCH (dB) 0.2 0.3 07208-035 0 -0.1 0 -1.00 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 QUADRATURE PHASE ERROR (Degrees) Figure 35. IQ Gain Mismatch Distributions, fRF = 2700 MHz Figure 38. IQ Quadrature Phase Error Distributions, fRF = 2700 MHz Rev. 0 | Page 12 of 28 ADL5382 CIRCUIT DESCRIPTION The ADL5382 can be divided into five sections: the local oscillator (LO) interface, the RF voltage-to-current (V-to-I) converter, the mixers, the differential emitter follower outputs, and the bias circuit. A detailed block diagram of the device is shown in Figure 39. BIAS V-TO-I CONVERTER The differential RF input signal is applied to a resistively degenerated common base stage, which converts the differential input voltage to output currents. The output currents then modulate the two half frequency LO carriers in the mixer stage. MIXERS IHI ILO LOIP RFIP RFIN POLYPHASE QUADRATURE PHASE SPLITTER LOIN The ADL5382 has two double-balanced mixers: one for the in-phase channel (I channel) and one for the quadrature channel (Q channel). These mixers are based on the Gilbert cell design of four cross-connected transistors. The output currents from the two mixers are summed together in the resistive loads that then feed into the subsequent emitter follower buffers. EMITTER FOLLOWER BUFFERS The output emitter followers drive the differential I and Q signals off-chip. The output impedance is set by on-chip 25 series resistors that yield a 50 differential output impedance for each baseband port. The fixed output impedance forms a voltage divider with the load impedance that reduces the effective gain. For example, a 500 differential load has 1 dB lower effective gain than a high (10 k) differential load impedance. QHI QLO Figure 39. Block Diagram 07208-039 The LO interface generates two LO signals at 90 of phase difference to drive two mixers in quadrature. RF signals are converted into currents by the V-to-I converters that feed into the two mixers. The differential I and Q outputs of the mixers are buffered via emitter followers. Reference currents to each section are generated by the bias circuit. A detailed description of each section follows. BIAS CIRCUIT A band gap reference circuit generates the proportional-toabsolute temperature (PTAT) as well as temperature-independent reference currents used by different sections. The mixer current can be reduced via an external resistor between the BIAS pin and ground. When the BIAS pin is open, the mixer runs at maximum current and therefore the greatest dynamic range. The mixer current can be reduced by placing a resistance to ground; therefore, reducing overall power consumption, noise figure, and IIP3. The effect on each of these parameters is shown in Figure 10, Figure 13, and Figure 14. LO INTERFACE The LO interface consists of a polyphase quadrature splitter followed by a limiting amplifier. The LO input impedance is set by the polyphase, which splits the LO signal into two differential signals in quadrature. Each quadrature LO signal then passes through a limiting amplifier that provides the mixer with a limited drive signal. For optimal performance, the LO inputs must be driven differentially. Rev. 0 | Page 13 of 28 ADL5382 APPLICATIONS INFORMATION BASIC CONNECTIONS Figure 41 shows the basic connections schematic for the ADL5382. LOCAL OSCILLATOR (LO) INPUT For optimum performance, the LO port should be driven differentially through a balun. The recommended balun is the M/A-COM ETC1-1-13. The LO inputs to the device should be ac-coupled with 1000 pF capacitors. The LO port is designed for a broadband 50 match from 700 MHz to 2.7 GHz. The LO return loss can be seen in Figure 20. Figure 40 shows the LO input configuration. LO INPUT 8 POWER SUPPLY The nominal voltage supply for the ADL5382 is 5 V and is applied to the VPA, VPB, VPL, and VPX pins. Ground should be connected to the COM, CML, and CMRF pins. The exposed paddle on the underside of the package should also be soldered to a low thermal and electrical impedance ground plane. If the ground plane spans multiple layers on the circuit board, these layers should be stitched together with nine vias under the exposed paddle. The Application Note AN-772 discusses the thermal and electrical grounding of the LFCSP in detail. Each of the supply pins should be decoupled using two capacitors; recommended capacitor values are 100 pF and 0.1 F. LOIP ETC1-1-13 1000pF 9 LOIN 07208-040 1000pF Figure 40. Differential LO Drive The recommended LO drive level is between -6 dBm and +6 dBm. The applied LO frequency range is between 700 MHz and 2.7 GHz. RFC ETC1-1-13 1000pF 33nH 1000pF 33nH VPOS 24 CMRF 23 CMRF 22 RFIP 21 RFIN 20 CMRF 19 VPX 1 VPA 0.1F 100pF VPB 18 100pF VPB 17 QHI 16 QHI QLO IHI ILO VPOS 0.1F 2 COM 3 BIAS 4 VPL VPOS 0.1F 100pF LOIN LOIP ADL5382 QLO 15 IHI 14 COM 5 VPL 6 VPL CML CML 7 8 9 10 11 CML ILO 13 12 1000pF 1000pF ETC1-1-13 LO Figure 41. Basic Connections Schematic Rev. 0 | Page 14 of 28 07208-041 ADL5382 RF INPUT The RF inputs have a differential input impedance of approximately 50 . For optimum performance, the RF port should be driven differentially through a balun. The recommended balun is the M/A-COM ETC1-1-13. The RF inputs to the device should be ac-coupled with 1000 pF capacitors. Ground-referenced choke inductors must also be connected to RFIP and RFIN (the recommended value is 33 nH, Coilcraft 0603CS-33NX) for appropriate biasing. Several important aspects must be taken into account when selecting an appropriate choke inductor for this application. First, the inductor must be able to handle the approximately 40 mA of standing dc current being delivered from each of the RF input pins (RFIP, RFIN). The suggested 0603 inductor has a 600 mA current rating. The purpose of the choke inductors is to provide a very low resistance dc path to ground and high ac impedance at the RF frequency so as not to affect the RF input impedance. A choke inductor that has a selfresonant frequency greater than the RF input frequency ensures that the choke is still looking inductive and therefore has a more predictable ac impedance (jL) at the RF frequency. Figure 42 shows the RF input configuration. 33nH 21 RFIN The differential RF port return loss is characterized as shown in Figure 43. -10 -12 -14 -16 -18 -20 -22 -24 0.7 S11 (dB) 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 FREQUENCY (GHz) Figure 43. Differential RF Port Return Loss BASEBAND OUTPUTS The baseband outputs QHI, QLO, IHI, and ILO are fixed impedance ports. Each baseband pair has a 50 differential output impedance. The outputs can be presented with differential loads as low as 200 (with some degradation in gain) or high impedance differential loads (500 or greater impedance yields the same excellent linearity) that is typical of an ADC. The TCM9-1 9:1 balun converts the differential IF output to singleended. When loaded with 50 , this balun presents a 450 load to the device. The typical maximum linear voltage swing for these outputs is 2 V p-p differential. The bias level on these pins is equal to VPOS - 2.8 V. The output 3 dB bandwidth is 370 MHz. Figure 44 shows the baseband output configuration. QHI 16 QHI 1000pF ETC1-1-13 1000pF 22 RFIP RF INPUT 33nH 07208-042 Figure 42. RF Input QLO 15 QLO IHI 14 IHI ILO 13 ILO Figure 44. Baseband Output Configuration Rev. 0 | Page 15 of 28 07208-044 07208-043 ADL5382 ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE EVM is a measure used to quantify the performance of a digital radio transmitter or receiver. A signal received by a receiver would have all constellation points at the ideal locations; however, various imperfections in the implementation (such as magnitude imbalance, noise floor, and phase imbalance) cause the actual constellation points to deviate from the ideal locations. The ADL5382 shows excellent EVM performance for various modulation schemes. Figure 45 shows the EVM performance of the ADL5382 with a 16 QAM, 200 kHz low IF. 0 -5 -10 -15 0 -5 -10 -15 EVM (dB) -20 -25 -30 -35 -40 -45 0 5 10 07208-046 07208-047 -50 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 RF INPUT POWER (dBm) Figure 46. EVM, RF = 2.6 GHz, IF = 0 Hz vs. RF Input Power for a 16 QAM 10 MHz Bandwidth Mobile WiMAX Signal (AC-Coupled Baseband Outputs) EVM (dB) -20 -25 -30 -35 -40 -45 -75 -65 -55 -45 -35 -25 -15 -5 07208-045 Figure 47 exhibits multiple W-CDMA low-IF EVM performance curves over a wide RF input power range into the ADL5382. In the case of zero-IF, the noise contribution by the vector signal analyzer becomes predominant at lower power levels, making it difficult to measure SNR accurately. 0 -5 RF INPUT POWER (dBm) -50 -85 -10 -15 EVM (dB) Figure 45. EVM, RF = 900 MHz, IF = 200 kHz vs. RF Input Power for a 16 QAM 160 ksym/s Signal -20 -25 -30 -35 -40 -45 0Hz 5MHz Figure 46 shows the zero-IF EVM performance of a 10 MHz IEEE 802.16e WiMAX signal through the ADL5382. The differential dc offsets on the ADL5382 are in the order of a few millivolts. However, ac coupling the baseband outputs with 10 F capacitors eliminates dc offsets and enhances EVM performance. With a 10 MHz BW signal, 10 F ac coupling capacitors with the 500 differential load results in a high-pass corner frequency of ~64 Hz, which absorbs an insignificant amount of modulated signal energy from the baseband signal. By using ac-coupling capacitors at the baseband outputs, the dc offset effects, which can limit dynamic range at low input power levels, can be eliminated. 2.5MHz 7.5MHz -50 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 RF INPUT POWER (dBm) Figure 47. EVM, RF = 1900 MHz, IF = 0 Hz, 2.5 MHz, 5 MHz, and 7.5 MHz vs. RF Input Power for a W-CDMA Signal (AC-Coupled Baseband Outputs) Rev. 0 | Page 16 of 28 ADL5382 COSLOt 0 IF IF -IF 0 +IF -90 0 +IF +90 LSB LO USB -IF SINLOt 0 +IF 0 0 +IF 07208-048 Figure 48. Illustration of the Image Problem LOW IF IMAGE REJECTION The image rejection ratio is the ratio of the intermediate frequency (IF) signal level produced by the desired input frequency to that produced by the image frequency. The image rejection ratio is expressed in decibels. Appropriate image rejection is critical because the image power can be much higher than that of the desired signal, thereby plaguing the down conversion process. Figure 48 illustrates the image problem. If the upper sideband (lower sideband) is the desired band, a 90 shift to the Q channel (I channel) cancels the image at the lower sideband (upper sideband). Phase and gain balance between I and Q channels are critical for high levels of image rejection. Figure 49 shows the excellent image rejection capabilities of the ADL5382 for low IF applications, such as W-CDMA. The ADL5382 exhibits image rejection greater than 45 dB over a broad frequency range. 70 2.5MHz LOW IF 60 5MHz LOW IF EXAMPLE BASEBAND INTERFACE In most direct conversion receiver designs, it is desirable to select a wanted carrier within a specified band. The desired channel can be demodulated by tuning the LO to the appropriate carrier frequency. If the desired RF band contains multiple carriers of interest, the adjacent carriers would also be down converted to a lower IF frequency. These adjacent carriers can be problematic if they are large relative to the wanted carrier as they can overdrive the baseband signal detection circuitry. As a result, it is often necessary to insert a filter to provide sufficient rejection of the adjacent carriers. It is necessary to consider the overall source and load impedance presented by the ADL5382 and ADC input to design the filter network. The differential baseband output impedance of the ADL5382 is 50 . The ADL5382 is designed to drive a high impedance ADC input. It may be desirable to terminate the ADC input down to lower impedance by using a terminating resistor, such as 500 . The terminating resistor helps to better define the input impedance at the ADC input at the cost of a slightly reduced gain (see the Circuit Description section for details on the emitter-follower output loading effects). The order and type of filter network depends on the desired high frequency rejection required, pass-band ripple, and group delay. Filter design tables provide outlines for various filter types and orders, illustrating the normalized inductor and capacitor values for a 1 Hz cutoff frequency and 1 load. After scaling the normalized prototype element values by the actual desired cut-off frequency and load impedance, the series reactance elements are halved to realize the final balanced filter network component values. IMAGE REJECTION (dB) 50 40 30 20 10 0 700 7.5MHz LOW IF RF FREQUENCY (MHz) Figure 49. Image Rejection vs. RF Frequency for a W-CDMA Signal, IF = 2.5 MHz, 5 MHz, and 7.5 MHz 07208-049 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 Rev. 0 | Page 17 of 28 ADL5382 As an example, a second-order Butterworth, low-pass filter design is shown in Figure 50 where the differential load impedance is 500 and the source impedance of the ADL5382 is 50 . The normalized series inductor value for the 10-to-1, load-to-source impedance ratio is 0.074 H, and the normalized shunt capacitor is 14.814 F. For a 10.9 MHz cutoff frequency, the single-ended equivalent circuit consists of a 0.54 H series inductor followed by a 433 pF shunt capacitor. The balanced configuration is realized as the 0.54 H inductor is split in half to realize the network shown in Figure 50. RS = 50 LN = 0.074H NORMALIZED SINGLE-ENDED CONFIGURATION RS = 0.1 RL RS = 50 VS 0.54H DENORMALIZED SINGLE-ENDED EQUIVALENT Figure 51 and Figure 52 show the measured frequency response and group delay of the filter. 10 5 MAGNITUDE RESPONSE (dB) 0 -5 -10 VS CN 14.814F RL= 500 -15 fC = 1Hz 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 FREQUENCY (MHz) Figure 51. Sixth-Order Baseband Filter Response 433pF RL= 500 900 800 RS = 25 2 VS fC = 10.9MHz 0.27H BALANCED CONFIGURATION RL 2 = 250 RL = 250 2 700 600 500 400 300 200 07208-052 433pF RS = 25 2 0.27H Figure 50. Second-Order Butterworth, Low-Pass Filter Design Example A complete design example is shown in Figure 53. A sixth-order Butterworth differential filter having a 1.9 MHz corner frequency interfaces the output of the ADL5382 to that of an ADC input. The 500 load resistor defines the input impedance of the ADC. The filter adheres to typical direct conversion W-CDMA applications, where 1.92 MHz away from the carrier IF frequency, 1 dB of rejection is desired and 2.7 MHz away 10 dB of rejection is desired. 07208-050 DELAY (ns) 100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 FREQUENCY (MHz) Figure 52. Sixth-Order Baseband Filter Group Delay Rev. 0 | Page 18 of 28 07208-051 -20 ADL5382 RFC ETC1-1-13 1000pF 33nH 1000pF 33nH CAC 10F 27H 27H 10H 270pF 100pF 68pF 24 23 22 21 20 19 RFIN RFIP CMRF CMRF CMRF VPX 1 VPA 0.1F 100pF VPB 18 100pF VPB 17 QHI 16 VPOS 0.1F CAC 10F 2 COM 3 BIAS 27H 27H 10H ADL5382 4 VPL VPOS 0.1F 100pF 5 VPL QLO 15 IHI 14 LOIN LOIP COM CML CML CML 6 VPL ILO 13 CAC 10F 27H 27H 10H 7 8 9 10 11 12 500 500 VPOS 1000pF 1000pF ETC1-1-13 CAC 10F ADC INPUT 07208-053 270pF 100pF 27H 27H 10H LO Figure 53. Sixth-Order Low-Pass Butterworth, Baseband Filter Schematic Rev. 0 | Page 19 of 28 68pF ADC INPUT ADL5382 As the load impedance of the filter increases, the filter design becomes more challenging in terms of meeting the required rejection and pass band specifications. In the previous WCDMA example, the 500 load impedance resulted in the design of a sixth-order filter that has relatively large inductor values and small capacitor values. If the load impedance is 200 , the filter design becomes much more manageable. As shown in Figure 54, the resultant inductor and capacitor values become much more practical. 10H 8H 5 MAGNITUDE RESPONSE (dB) 0 -5 -10 -15 680pF 100pF 200 50 0.6 1.0 1.4 1.8 2.2 2.6 3.0 3.4 3.8 FREQUENCY (MHz) 07208-054 10H 8H Figure 55. Fourth-Order Low-Pass W-CDMA Filter Magnitude Response 900 800 700 600 500 400 300 200 100 0.2 Figure 54. Fourth-Order Low-Pass W-CDMA Filter Schematic Figure 55 and Figure 56 illustrate the magnitude response and group delay response of the fourth-order filter, respectively. DELAY (ns) 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 FREQUENCY (MHz) Figure 56. Fourth-Order Low-Pass W-CDMA Filter Group Delay Response Rev. 0 | Page 20 of 28 07208-056 07208-055 -20 0.2 ADL5382 CHARACTERIZATION SETUPS Figure 57 to Figure 59 show the general characterization bench setups used extensively for the ADL5382. The setup shown in Figure 59 was used to do the bulk of the testing and used sinusoidal signals on both the LO and RF inputs. An automated Agilent VEE program was used to control the equipment over the IEEE bus. This setup was used to measure gain, IP1dB, IIP2, IIP3, I/Q gain match, and quadrature error. The ADL5382 characterization board had a 9-to-1 impedance transformer on each of the differential baseband ports to do the differential-to-singleended conversion, which presented a 450 differential load to each baseband port, when interfaced with 50 test equipment. For all measurements of the ADL5382, the loss of the RF input balun (the M/A-COM ETC1-1-13 was used on RF input during characterization) was de-embedded. The two setups shown in Figure 57 and Figure 58 were used for making NF measurements. Figure 57 shows the setup for measuring NF with no blocker signal applied while Figure 58 was used to measure NF in the presence of a blocker. For both setups, the noise was measured at a baseband frequency of 10 MHz. For the case where a blocker was applied, the output blocker was at a 15 MHz baseband frequency. Note that great care must be taken when measuring NF in the presence of a blocker. The RF blocker generator must be filtered to prevent its noise (which increases with increasing generator output power) from swamping the noise contribution of the ADL5382. At least 30 dB of attention at the RF and image frequencies is desired. For example, assume a 915 MHz signal applied to the LO inputs of the ADL5382. To obtain a 15 MHz output blocker signal, the RF blocker generator is set to 930 MHz and the filters tuned such that there is at least 30 dB of attenuation from the generator at both the desired RF frequency (925 MHz) and the image RF frequency (905 MHz). Finally, the blocker must be removed from the output (by the 10 MHz low-pass filter) to prevent the blocker from swamping the analyzer. SNS CONTROL FROM SNS PORT OUTPUT AGILENT N8974A NOISE FIGURE ANALYZER RF GND VPOS CHAR BOARD HP 6235A POWER SUPPLY LO 6dB PAD ADL5382 Q I R1 50 INPUT IEEE LOW-PASS FILTER AGILENT 8665B SIGNAL GENERATOR IEEE PC CONTROLLER Figure 57. General Noise Figure Measurement Setup Rev. 0 | Page 21 of 28 07208-057 ADL5382 BAND-PASS TUNABLE FILTER R&S SMT03 SIGNAL GENERATOR BAND-REJECT TUNABLE FILTER 6dB PAD RF GND VPOS CHAR BOARD HP 6235A POWER SUPPLY LO Q R1 50 LOW-PASS FILTER R&S FSEA30 SPECTRUM ANALYZER ADL5382 6dB PAD I 6dB PAD BAND-PASS CAVITY FILTER HP87405 LOW NOISE PREAMP 07208-058 AGILENT 8665B SIGNAL GENERATOR Figure 58. Measurement Setup for Noise Figure in the Presence of a Blocker 3dB PAD RF AMPLIFIER RF IEEE 3dB PAD IN VP GND 3dB PAD AGILENT 11636A OUT 3dB PAD R&S SMT06 RF IEEE 6dB PAD R&S SMT06 RF IEEE Q 6dB PAD SWITCH MATRIX I 6dB PAD GND VPOS CHAR BOARD AGILENT E3631 PWER SUPPLY LO 6dB PAD ADL5382 IEEE AGILENT E8257D SIGNAL GENERATOR IEEE IEEE IEEE 07208-059 RF INPUT PC CONTROLLER R&S FSEA30 SPECTRUM ANALYZER HP 8508A VECTOR VOLTMETER Figure 59. General Characterization Setup Rev. 0 | Page 22 of 28 INPUT CHANNELS A AND B ADL5382 EVALUATION BOARD The ADL5382 evaluation board is available. The board can be used for single-ended or differential baseband analysis. The default configuration of the board is for single-ended baseband analysis. RFC T1 R8 L2 C11 C10 L1 R7 VPOS R1 C1 C2 24 23 22 21 20 19 RFIP RFIN CMRF CMRF CMRF VPX 1 VPA VPB 18 C8 VPB 17 QHI 16 R6 C9 R9 R14 VPOS 2 COM R2 3 BIAS 4 VPL VPOS C3 R3 C4 5 VPL Q OUTPUT OR QHI R15 T2 ADL5382 QLO 15 C12 IHI 14 R16 LOIN LOIP COM CML CML CML 6 VPL ILO 13 QLO R10 R11 R4 C13 R13 R5 T3 I OUTPUT OR IHI 7 8 9 10 11 12 C6 C7 T4 ILO R12 LO Figure 60. Evaluation Board Schematic Rev. 0 | Page 23 of 28 07208-060 ADL5382 Table 4. Evaluation Board Configuration Options Component VPOS, GND R1, R3, R6 C1, C2, C3, C4, C8, C9 C6, C7, C10, C11 R4, R5, R9 to R16 Function Power Supply and Ground Vector Pins. Power Supply Decoupling. Shorts or power supply decoupling resistors. These capacitors provide the required decoupling up to 2.7 GHz. AC Coupling Capacitors. These capacitors provide the required ac coupling from 700 MHz to 2.7 GHz. Single-Ended Baseband Output Path. This is the default configuration of the evaluation board. R14 to R16 and R4, R5, and R13 are populated for appropriate balun interface. R9, R10 and R11, R12 are not populated. Baseband outputs are taken from QHI and IHI. The user can reconfigure the board to use full differential baseband outputs. R9 to R12 provide a means to bypass the 9:1 TCM9-1 transformer to allow for differential baseband outputs. Access the differential baseband signals by populating R9 to R12 with 0 and not populating R4, R5, R13 to R16. This way the transformer does not need to be removed. The baseband outputs are taken from the SMAs of Q_HI, Q_LO, I_HI, and I_LO. Input Biasing. Inductance and resistance sets the input biasing of the common base input stage. The default value is 33 nH. IF Output Interface. TCM9-1 converts a differential high impedance IF output to a singleended output. When loaded with 50 , this balun presents a 450 load to the device. The center tap can be decoupled through a capacitor to ground. Decoupling Capacitors. C12 and C13 are the decoupling capacitors used to reject noise on the center tap of the TCM9-1. LO Input Interface. The LO is driven differentially. ETC1-1-13 is a 1:1 RF balun that converts the single-ended RF input to differential signal. RF Input Interface. ETC1-1-13 is a 1:1 RF balun that converts the single-ended RF input to differential signal. RBIAS. Optional bias setting resistor. See the Bias Circuit section to see how to use this feature. Default Condition Not applicable R1, R3, R6 = 0 (0603) C2, C4, C8 = 100 pF (0402) C1, C3, C9 = 0.1 F (0603) C6, C10, C11 = 1000 pF (0402) C7 = open R4, R5, R13 to R16 = 0 (0402) R9 to R12 = open L1, L2, R7, R8 T2, T3 L1, L2 = 33 nH (0603CS-33NX, Coilcraft) R7, R8 = 0 (0402) T2, T3 = TCM9-1, 9:1 (Mini-Circuits) C12, C13 = 0.1 F (0402) T4 = ETC1-1-13, 1:1 (M/A-COM) T1 = ETC1-1-13, 1:1 (M/A-COM) R2 = open C12, C13 T4 T1 R2 Rev. 0 | Page 24 of 28 ADL5382 07208-061 Figure 61. Evaluation Board Top Layer Figure 62. Evaluation Board Top Layer Silkscreen Rev. 0 | Page 25 of 28 07208-062 ADL5382 Figure 63. Evaluation Board Bottom Layer 07208-063 Figure 64. Evaluation Board Bottom Layer Silkscreen Rev. 0 | Page 26 of 28 07208-064 ADL5382 OUTLINE DIMENSIONS 4.00 BSC SQ 0.60 MAX 0.60 MAX 0.50 BSC 0.50 0.40 0.30 1.00 0.85 0.80 12 MAX 0.80 MAX 0.65 TYP 19 18 EXPOSED PAD 24 1 PIN 1 INDICATOR *2.45 2.30 SQ 2.15 6 PIN 1 INDICATOR TOP VIEW 3.75 BSC SQ (BO TTOMVIEW) 13 12 7 0.23 MIN 2.50 REF 0.05 MAX 0.02 NOM 0.20 REF COPLANARITY 0.08 SEATING PLANE 0.30 0.23 0.18 *COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2 EXCEPT FOR EXPOSED PAD DIMENSION Figure 65. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-24-2) Dimensions shown in millimeters ORDERING GUIDE Model ADL5382ACPZ-R7 1 ADL5382ACPZ-WP1 ADL5382-EVALZ1 1 Temperature Range -40C to +85C -40C to +85C Package Description 24-Lead LFCSP_VQ, 7" Tape and Reel 24-Lead LFCSP_VQ, Waffle Pack Evaluation Board Package Option CP-24-2 CP-24-2 Ordering Quantity 1,500 64 Z = RoHS Compliant Part. Rev. 0 | Page 27 of 28 ADL5382 NOTES (c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07208-0-3/08(0) T T Rev. 0 | Page 28 of 28 |
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